Tools and conventions
The tools chosen to draw the boards and write the Verilog, the firmware and the 65816 software, and the rules the project has set itself.
The tools
| Area | Tools |
|---|---|
| Circuit boards | KiCad 8 or later |
| FPGA | Gowin EDA, or the free toolchain Yosys, nextpnr-himbaechel and Apicula |
| Programming the 9K | openFPGALoader with a Tigard probe (JTAG at 1.8 V) |
| Simulation | Verilator or Icarus Verilog |
| Pico firmware | pico-sdk 2.x with TinyUSB |
| 65816 software | ca65 (from cc65) or 64tass |
The repository layout
| Folder | Contents |
|---|---|
docs/ | the specification, the register map, the timings, the decisions |
hardware/proto-v1/ | the validation board (KiCad) |
hardware/itx-v1/ | the Mini-ITX board (KiCad) |
fpga/sysctl-9k/ | the Verilog for the controller and the sound |
fpga/video-20k/ | the Verilog for the HDMI video |
firmware/pico/ | the Pico firmware (C) |
software/ | the boot code, the monitor, 65816 demos |
tools/ | tooling scripts |
What exists today: the specification, the README, the Tang Nano 9K pinout survey
(docs/tang-nano-9k-brochage.md, option set aside), the decision on the system controller
(docs/choix-controleur-systeme.md), JTAG programming (docs/jtag.md) and a first tool, tools/pin_budget.py, which totals the system
controller’s pins, with its tests.
The conventions
- Comments and documentation in French, code identifiers in English.
- In Verilog, active-low signals have the suffix
_n(resb_n,oe_n). - Each Verilog module has its own testbench; no FPGA code is considered valid without a simulation of the PHI2 timings.
- Any change to the pinout, the memory map or the expansion port is first recorded in the specification.
- No manufacturing file (Gerber, assembly bill of materials) without a full design rule check and without explicit approval.
- Anything marked “to be checked” is never assumed: it is checked against the official documentation, or stated as still unknown.