The processor and the bus
Three components form the heart of the machine: the processor, the memory, and the system controller that makes them work together. This trio is what the validation board must prove first.
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The W65C816S
The processor is a W65C816S from WDC, in a DIP40 or PLCC44 package, used in 65816 native mode (16 bits). It runs on 3.3 V, like the rest of the machine. At 3.3 V, its maximum speed is 8 MHz (a cycle of at least 125 ns); the first tests will run slower, between 2 and 4 MHz. With the chosen memory (see below), the effective speed will depend on the accesses: see Speed, estimated then measured.
The memory: 16 MB of PSRAM, no ROM
All the memory is made of two APS6404L PSRAMs of 8 MB each, that is 16 MB: the whole 24-bit address space of the 65816. A PSRAM is driven over a fast serial link with four data lines, QSPI. There is no ROM: the boot code is written into PSRAM before the processor starts.
The PSRAM is connected only to the 9K, which becomes the memory controller. The processor never sees it directly: on every access, the 9K reads or writes the PSRAM on its behalf, and stretches the high phase of the clock for the duration of the operation.
The first choice was a 2 MB parallel SRAM (IS61WV20488); the decision to move to 16 MB of PSRAM dates from 15 October 2026.
The system controller (“the 9K”), master of the bus
The system controller is a Gowin GW1NR-LV9QN88P FPGA, soldered directly on the board: it is the chip of Sipeed’s Tang Nano 9K, without the module. The specification still calls it “the 9K”. It:
- makes the processor’s PHI2 clock, with its PLL, from a 27 MHz crystal placed on the board;
- latches the bank (the upper 8 bits of the address) on every cycle;
- decodes addresses: it knows whether an access targets memory, its own registers, video, the Pico or the expansion port;
- serves the memory: it is the only device connected to the PSRAM, over QSPI;
- produces the sound and performs memory transfers (DMA).
The bus rule
The 65816 has only 16 address pins. During the clock’s low phase, it places the bank (A16 to A23) on its data pins D0 to D7. Hence three rules:
- Nobody other than the processor drives the data bus during the low phase.
- The 9K latches the bank just before the clock rises.
- During the high phase, the 9K serves the access: it reads or writes the PSRAM and, on a read, places the data on D0 to D7; it stretches the high phase for the duration of the access.
Finally, every access is qualified by the processor’s VDA or VPA signals: cycles where neither is active are “phantom” cycles, which the 9K ignores.
Constraints not to forget
- RDY is never actively driven as an output: the 65816’s
WAIinstruction itself pulls this line low. It is connected to the 9K as open drain, with a pull-up resistor. - IRQB and NMIB, the two interrupt lines, are pulled as open drain by the 20K, the Pico and the expansion port, without going through the 9K: this is a “wired-AND”.
- ABORTB must have a pull-up resistor to 3.3 V.
- At start-up, RESB and BE are pulled to ground: the processor stays in reset and off the bus until the 9K releases it.
The full pinout is in W65C816S pinout.
Why a soldered chip rather than a module
The project first planned the Tang Nano 9K module on headers. Surveying its pinout, on 15 October 2026, showed that it offers only 29 inputs/outputs at 3.3 V usable directly (37 after modifying the module). The controller needs 47: the 44 of the initial budget, plus address lines A5 to A7, without which the 9K cannot address the SRAM during audio DMA. Even with the planned fallbacks (512 KB SRAM, codec on the Pico), it did not fit.
Seven options were compared: the Tang Nano 9K and 20K modules, the soldered GW1NR-9 chip, a soldered ECP5 FPGA, the Tang Primer 20K module, Digilent’s Cmod A7, the RP2350B. Decision of 15 October 2026: solder the Tang Nano 9K’s chip directly on the board.
- Nothing changes on the logic side: same Verilog, same tools (Gowin EDA, or Yosys, nextpnr and Apicula), same amount of logic (8,640 LUTs).
- All 71 inputs/outputs of the package become available, within the voltage limits of their banks (see below).
- The fallbacks are dropped: the codec stays on the 9K, and DMA has all the address lines.
- Component assembly by JLCPCB was already planned: a QFN package cannot be soldered by hand.
Speed, estimated then measured
The processor provides the full address (bank included) 40 ns after the falling edge of the clock. The 9K can therefore start the PSRAM access as early as the low phase, then stretch the clock until the data is ready. A model, drawn from the data sheets, gives the processor’s effective speed according to the frequency of the QSPI link:
| QSPI link | Isolated read | Write | Sequential read |
|---|---|---|---|
| 50 MHz | 2.27 MHz | 3.33 MHz | 7.14 MHz |
| 66 MHz | 2.87 MHz | 4.22 MHz | 8.00 MHz |
| 84 MHz | 3.49 MHz | 5.13 MHz | 8.00 MHz |
| 100 MHz | 4.00 MHz | 5.88 MHz | 8.00 MHz |
| 109 MHz | 4.27 MHz | 6.28 MHz | 8.00 MHz |
- Isolated accesses (data, jumps) top out at around 4 MHz.
- Sequential reads (the instruction stream) reach 8 MHz from a 66 MHz link upwards, if the 9K keeps the read open from one byte to the next. This is the main lever, and it only takes Verilog.
- The average speed depends on the mix of accesses in each program.
That mix was recorded on a real 65816 program: the OricOS kernel, run under the Oric 2 project’s Phosphoric emulator (78,056 instructions).
| Type of access | Share |
|---|---|
| read following the previous one (served as a burst) | 62.7% |
| isolated read | 28.0% |
| write | 6.5% |
| input/output | 2.8% |
Hence an expected average speed, on this program, of about 6 MHz with a 100 MHz QSPI link, and 5 MHz at 66 MHz (4.3 MHz at 50 MHz; 6.3 MHz at 109 MHz).
The pin budget
A first count gave 53 general-purpose inputs/outputs, assuming every bank of the chip at 3.3 V. That assumption was wrong. Gowin’s documentation (UG803) shows that, on this package, bank 3 also powers a small PSRAM built into the FPGA (unrelated to the machine’s 16 MB): its voltage is fixed at 1.8 V. Its pins therefore cannot connect directly to the 3.3 V bus.
| Package inputs/outputs | at 3.3 V | at 1.8 V (bank 3) |
|---|---|---|
| general-purpose | 38 | 15 |
| configuration pins usable as inputs/outputs | 7 | — |
| configuration pins whose use is not confirmed | 2 | — |
| reserved (JTAG, modes, crystal input…) | 1 | 8 |
Two decisions then made it fit: the audio codec at 1.8 V on bank 3, and PSRAM instead of SRAM.
| Need at 3.3 V | Pins |
|---|---|
| data D0 to D7 | 8 |
| address A0 to A15 | 16 |
| control inputs (RWB, VDA, VPA, /BUSREQ) | 4 |
| outputs (PHI2, RESB, RDY, BE) | 4 |
| QSPI PSRAM (clock, 4 data lines, 2 selects) | 7 |
| video and Pico selects | 2 |
| expansion select (/IOSEL) | 1 |
| total at 3.3 V | 42 out of 45 available: margin of 3 (5 with the unconfirmed pins) |
With the codec’s 8 pins at 1.8 V (below), the 9K uses 50 pins in all.
The first budget counted “4 pins for I²S”: it left out the codec’s master clock, its I²C control and its reset. And the PSRAM replaces the SRAM’s 7 pins (upper address bits, /OE, /WE) with the 7 of its QSPI link, while removing the expansion’s /MEMSEL select. The 7 remaining bank 3 pins must never be connected to a 3.3 V component: the schematic will be checked per voltage domain.
Variants of the chip whose banks all accept 3.3 V exist, but were not in stock at LCSC on 15 October 2026. The choice of soldering the FPGA on the board still stands.
What the board gets in addition
Without the module, the board must provide what the Tang Nano 9K gave the chip: a 1.2 V regulator for its core, a 1.8 V regulator for bank 3 and the FPGA’s internal PSRAM, the 27 MHz crystal, a 1.8 V 1 × 8 JTAG connector and decoupling capacitors. The FPGA configures itself from its internal flash, programmed over JTAG. As JTAG sits on bank 3, at 1.8 V, the project chose a probe that accepts that voltage, the Tigard, driven by openFPGALoader (alternative: Digilent JTAG-HS2).
The full reasoning and comparison are in the repository: docs/choix-controleur-systeme.md.