Where the project stands
Project 816 is just starting: its specification is written, nothing has yet been drawn, coded or built. Here is what comes next, in the planned order.
Today
| Item | Status |
|---|---|
| Specification | written |
| System controller | GW1NR-9 FPGA soldered on the board; 42 pins at 3.3 V out of 45 (margin of 3) and the audio codec at 1.8 V |
| Memory | 16 MB of QSPI PSRAM, chosen on 15 October 2026; effective speed of about 4 MHz estimated, to be measured |
Register map (docs/registers.md) | version 0.1 proposed, to be validated |
| FPGA Verilog | not started |
| Pico firmware | not started |
| Schematics and boards | not started |
| 65816 software | not started |
The project is in Phase 1: preparing the validation board.
The tasks, in order
- ✅ Check the actual pinout of the Tang Nano 9K: done on 15 October 2026; the module does not have enough pins.
- ✅ Choose a solution: the Tang Nano 9K’s FPGA is soldered directly on the board (see The processor and the bus).
- ✅ Check the bank voltages in Gowin’s documentation: bank 3 is fixed at 1.8 V, and the need for 47 pins does not fit all at 3.3 V.
- ✅ Validate the audio codec at 1.8 V on bank 3: chosen on 15 October 2026 (8 pins).
- ✅ Choose a JTAG probe compatible with 1.8 V: the Tigard is chosen (Digilent JTAG-HS2 as an alternative), with a 1 × 8 connector on the board.
- ✅ Write the register map: version 0.1, proposed on 15 October 2026 (The register map); still to be validated.
- ✅ Measure the access mix of a real 65816 program: done on the OricOS kernel, under emulation.
- Measure the QSPI frequency sustained, with a PSRAM wired to the Tang Nano 20K at hand, then check the 9K’s chip with a timing analysis.
- Write the 9K Verilog: clock and PHI2 (with its clock stretching), bank latching, decoding, QSPI PSRAM controller with a PSRAM simulation model, start-up handling, each with its testbench.
- Draw the validation board schematic: processor, PSRAM, 9K FPGA and its power supplies, JTAG, headers, and access for a logic analyser.
- Route the validation board in 2 layers, with a check against the manufacturer’s rules (JLCPCB).
- Write a minimal Pico firmware: loading the boot code into PSRAM (through the 9K), serial console.
- Write a 65816 test program: a test of the whole 16 MB of memory.
- Only after validation: the schematic and routing of the Mini-ITX board.
The points still open
The specification refuses to guess. These points are marked as to be checked or to be decided:
- the register map v0.1, to be validated (sound cores, boot loading by the Pico, video modes);
- the QSPI link frequency the 9K will reach, and so the processor’s effective speed (to be measured on the Tang Nano 20K, then by timing analysis for the 9K’s chip);
- a PSRAM constraint (tCEM, maximum duration of a selection) to be checked on its data sheet;
- using the FPGA’s pins 53 and 54 as inputs/outputs;
- routing the QFN88 package (0.4 mm pitch) on a 2-layer board, not checked;
- the FPGA’s stock at LCSC (168 parts on 15 October 2026);
- the position of the expansion slot on the Mini-ITX board, and the exact dimensions, to be checked against an official template;
- the pin numbers of the processor in the PLCC44 package (same signals as in DIP40);
- the choice of sound cores: FM, PSG, SID or POKEY;
- the detailed register map of each block;
- the availability at LCSC of the FE2.1 USB hub and the TLV320AIC3254 codec.
This wiki follows the specification: it will be updated as these points are settled.