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Project 816 for complete beginners

No need to know what an FPGA is. In a few diagrams, here is what Project 816 will be, how its parts work together, and where it stands today.

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1. The idea: a 16-bit computer of today

In the 1980s, microcomputers were built around a processor, memory and a few specialised chips for graphics and sound. Project 816 takes up this idea with present-day parts:

  • a real W65C816S processor, still made by WDC: the 16-bit version of the famous 6502;
  • 16 MB of memory (PSRAM), all that the processor can address;
  • in place of the specialised chips of the past, FPGAs: chips whose circuits you design yourself, by writing a program that describes them;
  • a Raspberry Pi Pico 2 W for everything modern: USB, SD card, Wi-Fi;
  • a board in the Mini-ITX format, to house the machine in an ordinary PC case.

2. Who does what

Who does what in Project 816A real W65C816S shares its bus with three programmable devices: the system controller, a GW1NR-9 FPGA soldered on the board and bus master (clock, bank, decoding, sound, DMA), the Tang Nano 20K for HDMI video and the Pico 2 W for USB, the SD card, Wi-Fi and the clock. An expansion port completes the bus. The slaves expose only 32 registers each. The memory, 16 MB of QSPI PSRAM, and the 1.8 V audio codec are connected to the 9K alone.65816 busAudio codecTLV320AIC3254at 1.8 VI²S + I²C, bank 3W65C816Sthe 16-bit processor≈ 4 MHz expected“9K” controllerGW1NR-9 FPGA, solderedclock, bank, decoding,memory, sound, DMATang Nano 20KVERA-like videoHDMI output,video memory in its SDRAMPico 2 Winput/outputUSB, SD card,Wi-Fi, clockbus master32 registers32 registers16 MB PSRAM2 × APS6404L, no ROMconnected to the 9K aloneQSPIExpansion port2 × 25 header74LVC245 buffersA 3.3 V bus, with no level shifters; only the 9K's bank 3 runs at 1.8 V. Dots mark the taps on the bus.
The processor in the centre, on its bus with three programmable devices; the memory is connected only to the “9K” controller, which serves it on the processor’s behalf.
  • The W65C816S runs the programs. It is the machine’s only real “retro” processor.
  • The PSRAM of 16 MB is all the memory: there is no ROM. Only the 9K is connected to it, and it performs the accesses for the processor. The boot program is copied into memory before the processor starts.
  • The system controller, nicknamed “the 9K”, is the conductor: an FPGA soldered directly on the board (the Tang Nano 9K’s chip, without its module). It generates the processor’s clock, decides who talks on the bus, drives the memory and produces the sound.
  • The Tang Nano 20K (a larger FPGA) is the graphics card: it generates the picture and sends it to an HDMI socket.
  • The Pico 2 W takes care of input and output: USB keyboard and mouse, microSD card, Wi-Fi, clock, serial link.

The 20K and the Pico do not see all of the memory: each offers the processor only 32 registers, a small window through which it is given orders.

3. 16 bits and their 16 MB

The 6502 of the 1980s could see only 64 KB of memory. The 65816 sees 16 MB, divided into 256 banks of 64 KB. Project 816 fills all of them with memory: two 8 MB chips.

The Project 816 memory mapThe 65816 addresses 16 MB in 256 banks of 64 KB, and all of them are RAM: banks $00 to $7F in the first 8 MB PSRAM, $80 to $FF in the second. In bank $00, four 256-byte pages, from $9C00 to $9FFF, are reserved for the registers of the 9K, the video, the Pico and the expansion port; everything else is RAM, vectors included.The 65816's 16 MB256 banks of 64 KB, all RAM$00bank 0: detail on the right$01–$7FRAM: 1st PSRAM (CS0#)$80–$FFRAM: 2nd PSRAM (CS1#)Bank $00RAM and four register pages$0000–$9BFFRAM$9C009K: sound, interrupts, DMA$9D00video (Tang Nano 20K)$9E00Pico: SD, USB, Wi-Fi, clock$9F00expansion port$A000–$FFFFRAM, including the 65816 vectorsEach block exposes 32 registers, repeated across its 256-byte page.(not to scale)
The memory map: what is found at each address. The registers of the 9K, the video, the Pico and the expansion occupy four small pages in the first bank.

4. A 65816 trick: the bank on the data lines

To address 16 MB, you need 24 address bits. Yet the 65816 package has only 16 address pins. The trick: during the first half of each cycle, it places the 8 missing bits (the bank) on its data pins. The 9K must capture them at the right moment, before those same pins are used for the data.

One 65816 bus cycleDuring the low phase of PHI2, the processor puts the bank, the top 8 bits of the address, on the data wires D0 to D7; the 9K latches it just before the clock rises. During the high phase, the same wires carry the data: the 9K reads or writes the PSRAM over QSPI and stretches the high phase for the length of that access.PHI2low phasehigh phaseA0–A15address A0–A15 (low 16 bits)D0–D7bank A16–A23, set by the CPUdata: driven by the 9K or by the CPUthe 9K latches the bank herethe 9K accesses the PSRAM and stretches the high phaseOnly cycles flagged by VDA or VPA count; phantom cycles are ignored.
A bus cycle: first the bank on the data lines, then the data itself. This is the first thing the validation board will have to prove.

5. Three stages, in order

The project advances in phases, and moves on to the next only once the previous one works on real hardware:

The three phases of Project 816Phase 1: a 100 × 100 mm, 2-layer validation board with the processor, the PSRAM and the 9K. Phase 2: the 170 × 170 mm, 4-layer Mini-ITX board with the whole machine. Phase 3: software. The project is at the phase 1 specification. No board is ordered until the previous phase has been validated on real hardware.Phase 1validation board≈ 100 × 100 mm, 2 layersCPU, PSRAM, 9KPhase 2Mini-ITX board170 × 170 mm, 4 layersthe whole machinePhase 3softwaremonitor, BASIC or system,toolswe are here: the specificationNo board is ordered until the previous phase has been validated on real hardware.
A small validation board first, the large Mini-ITX board next, and the software last.

6. The final board

In the absence of a photo, here is the planned layout of the Mini-ITX board: the sockets at the back, as on a PC, and the heart of the machine in the centre.

The planned Mini-ITX board, seen from aboveIndicative plan of the 170 × 170 mm board. On the rear edge: the Tang Nano 20K with its HDMI socket, three USB-A blocks, the microSD reader, the audio jacks and the double DE-9. In the centre: the processor, the 9K and the PSRAM, grouped for short traces. On the left: the expansion port; on the right: the ATX connector and power; at the front: audio, reset, LEDs, USB and the front-panel connector. Four mounting holes in the corners.rear edge (towards the outside of the case)front edge (front panel)20K + HDMIUSB-A × 3microSDjacksDE-9 × 2CPU · 9K · PSRAMgrouped in the centrefor short tracesexpansion port and buffers24-pin ATX and powerHD Audio · reset · LEDs · front USB · front panelIndicative plan: dimensions and expansion slot to be checked on an official Mini-ITX template.
The Mini-ITX board as described by the specification. The exact dimensions are still to be checked against an official template before the board is drawn.

7. In short

QuestionShort answer
What is it?A neo-retro 16-bit microcomputer, in the Mini-ITX format.
With which processor?A real W65C816S, at 3.3 V; about 6 MHz on average (estimate, 4 to 8 depending on the accesses).
And the rest?Two FPGAs (control and sound, soldered on the board; HDMI video, as a module) and a Pico 2 W (USB, SD, Wi-Fi, clock).
Does it exist?Not yet: the specification is written, the validation board is the next step.
What next?See Where the project stands.

The technical words are explained in the glossary.

Sources in the repository : docs/SPEC.md, README.md.